HOW Series “Deep Dive”: Webinars on Performance Optimization – 2017 Edition

 

In a Nutshell

HOW Series “Deep Dive” is a free Web-based training on parallel programming and performance optimization on Intel architecture. The workshop includes 20 hours of instruction and up to 2 weeks of remote access to dedicated training servers for hands-on exercises. This training is free to everyone thanks to Intel’s sponsorship.

 

You can get trained in one of the two ways:

Self-paced: Start Right Now

You can access the video recordings of lectures, slides of presentations and code of practical exercises on this page using a free Colfax Research account.

This option is free and open to everyone, however, self-paced study does not give you the benefits that you get by joining a workshop (which is also free, but tied to specific dates).


 

Join a Workshop: Interact and Practice

You can join one of the 2-week long HOW series workshops to get these additional benefits:

  • Access a dedicated computing cluster to run exercises
  • Get reminders to join daily online broadcasts of recordings
  • Live chat with instructor during broadcasts
  • Receive a certificate of completion


 

Upcoming Workshops:

(the 10-day workshops occurring in different months have the same agenda)

October 2017
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    — 16:00 GMT (for America/Europe)
November 2017
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    — 04:00 GMT (for Asia/Pacific) + 16:00 GMT on same day

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Registration:

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xeon-phi-in-server-1800

Why Attend the HOW Series

Here is what the HOW Series training will deliver for you:

Learn Modern Code

Are you realizing the payoff of parallel processing? Are you aware that without code optimization, computational applications may perform orders of magnitude worse than they are supposed to?

The Web-based HOW Series training provides the extensive knowledge needed to extract more of the parallel compute performance potential found in both Intel® Xeon® and Intel® Xeon Phi™ processors and coprocessors. Course materials and practical exercises are appropriate for developers beginning their journey to parallel programming, with enough detail to also cater to high-performance computing experts.

Jump to detailed descriptions of sessions to see what you will learn.

Practice New Skills

The HOW series is an experiential learning program because you get to see code optimization performed live and also get to practice it with your own hands. The workshop consists of instructional and hands-on self-study components:

The instructional part of each workshop consists of 10 lecture sessions. Each session presents 1 hour of theory and 1 hour of practical demonstrations. Lectures can be viewed live by joining live broadcast, or offline as streaming video.

In the self-study part, for the duration of the workshop attendees are provided with remote access over SSH to a Linux-based cluster of training servers. These machines feature Intel Xeon Phi processors (KNL) and Intel software development tools. Students can use these training servers to run exercises provided in the course or experiment with their own applications.

Receive Certificate

certificate

Attendees of these workshops may receive a certificate of completion. The certificate states the Fundamental level of accomplishment in the Parallel Programming Track.

Attending at least 6 out of 10 live broadcast sessions is required to receive the certificate. Certificates are delivered via email within 7 days after the last webinar.

What HOW Series Graduates are Saying:

"An un-parallel resource for learning trade skills of using Intel Xeon Phi platform for Parallel Computing. What makes this program all the more engaging is its focus on the 'doing' aspect as there is no substitute to 'learning by doing'."

Gaurav Verma
HOW attendee


"I am a physicist working with Monte Carlo models of particle transport on matter. My main working language is Fortran and I was able to follow the course without problems. The course gave me all the tools needed to start working with the Intel Xeon Phi MICs."

Edgardo Doerner
HOW attendee


"This is a very well thought out course that gradually introduces the important concepts. The presenter and his team are experts with a lot of experience as evident from the lectures. The live demos for optimizations are very educative and well executed."

Vikram K. Narayana
HOW attendee

Course Roadmap

Instructor Bio

Andrey Vladimirov Andrey Vladimirov, Ph. D., is Head of HPC Research at Colfax International. His primary interest is the application of modern computing technologies to computationally demanding scientific problems. Prior to joining Colfax, A. Vladimirov was involved in computational astrophysics research at Stanford University, North Carolina State University, and the Ioffe Institute (Russia), where he studied cosmic rays, collisionless plasmas and the interstellar medium using computer simulations. He is the lead author of the book "Parallel Programming and Optimization with Intel Xeon Phi Coprocessors", a regular contributor to the online resource Colfax Research, author of invited papers in "High Performance Parallelism Pearls" and Intel Xeon Phi Processor High Performance Programming: Knights Landing Edition, and an author or co-author of over 10 peer-reviewed publications in the fields of theoretical astrophysics and scientific computing.

Prerequisites

remote-access We assume that you know the fundamentals of programming in C or C++ in Linux. If you are not familiar with Linux, read a basic tutorial such as this one. We assume that you know how to use a text-based terminal to manipulate files, edit code and compile applications.

Remote Access for Hands-On Exercises

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All registrants will receive remote access to a cluster of training servers. The compute nodes in the cluster are based on Intel Xeon Phi x200 family processors (formerly KNL), and additional nodes with Intel Xeon processors and Intel Xeon Phi coprocessors (KNC) are available. Intel software development tools are provided in the cluster under the Evaluation license.

Remote access is be granted a few days before the start of the series. It is active for the entire duration the training, including nights and weekends. However, technical support is available only during normal business hours Pacific time.

You do not have to use remote access to the Colfax Cluster to participate in the hands-on part. During live webinars, the instructor will demonstrate the discussed programming exercises. You can either follow along or use your own computing system (Intel compilers required).

Slides, Code and Video:

Code

code-download Practical exercises in this training were originally published as supplementary code for Programming and Optimization for Intel Xeon Phi Coprocessors. Since then, we have re-released them under the MIT license and posted on GitHub with the latest updates.

You can download the labs as a ZIP archive or clone from GitHub:

git clone https://github.com/ColfaxResearch/HOW-Series-Labs.git

Video

Session 01
Intel Architecture and Modern Code

We introduce Intel Xeon and Intel Xeon Phi processors and discuss their features and purpose. We also begin an introduction to portable, future-proof parallel programming: thread parallelism, vectorization, and optimized memory access pattern. The hands-on part introduces Intel compilers and additional software for efficient solution of computational problems. The hands-on part illustrates the usage of the Colfax Cluster for programming exercises presented in the course.

Slides:  Colfax_HOW_Series_01.pdf (13 MB) — this file is available only to registered users. Register or Log In.

Session 02
Xeon Phi, Coprocessors, Omni-Path

We talk about high-bandwidth memory (MCDRAM) in Intel Xeon Phi processors and demonstrate programming techniques for using it. We also discuss the coprocessor form-factor of the Intel Xeon Phi platform, learning to use the native and the explicit offload programming models. The session introduces the high-bandwidth interconnects based on the Intel Omni-Path Architecture, and discusses its application in heterogeneous programming with offload over fabric.

Slides:  Colfax_HOW_Series_02.pdf (4 MB) — this file is available only to registered users. Register or Log In.

Session 03
Expressing Parallelism with Vectors

This session introduces data parallelism and automatic vectorization. Topics include: the concept of SIMD operations, history and future of vector instructions in Intel Architecture, including AVX-512, using intrinsics to vectorize code, automatic vectorization with Intel compilers for loops, expressions with array notations and SIMD-enabled functions. The hands-on part focuses on using the Intel compiler to perform automatic vectorization, diagnose its success, and making automatic vectorization happen when the compiler does not see opportunities for data parallelism.

Slides:  Colfax_HOW_Series_03.pdf (3 MB) — this file is available only to registered users. Register or Log In.

Session 04
Multi-threading with OpenMP

Crash-course on thread parallelism and the OpenMP framework. We will talk about using threads to utilize multiple processor cores, coordination of thread and data parallelism, using OpenMP to create threads and team them up to process loops and trees of tasks. You will learn to control the number of threads, variable sharing, loop scheduling modes, to use mutexes to protect race conditions, and implementing parallel reduction. The hands-on part demonstrates using OpenMP to parallelize serial computation and shows for-loops, variable sharing, mutexes and parallel reduction on an example application performing numerical integration.

Slides:  Colfax_HOW_Series_04.pdf (3 MB) — this file is available only to registered users. Register or Log In.

Session 05
Distributed Computing, MPI


The last session of the week is an introduction to distributed computing with the Message Passing Interface (MPI) framework. We illustrate the usage of MPI on standard processors as well as Intel Xeon Phi processors and heterogeneous systems with coprocessors. Inter-operation between Intel MPI and OpenMP is illustrated.

Slides:  Colfax_HOW_Series_05.pdf (6 MB) — this file is available only to registered users. Register or Log In.

Session 06
Optimization Overview: N-body

Here we begin the discussion of performance optimization. This episode lays out the optimization roadmap that classifies optimization techniques into five categories. The lecture part of demonstrates the application of some of the techniques from these 5 categories to an example application implementing the direct N-body simulation. The hands-on part of the episode demonstrates the optimization process for the N-body simulation and measures performance gains obtained on an Intel Xeon E5 processor and their scalability to an Intel Xeon Phi coprocessor (KNC) and processor (KNL).

Slides:  Colfax_HOW_Series_06.pdf (3 MB) — this file is available only to registered users. Register or Log In.

Session 07
Scalar Tuning, Vectorization

We start going into the details of performance tuning. The session will cover essential compiler arguments, control of precision and accuracy, unit-stride memory access, data alignment, padding and compiler hints, and the usage of strip-mining for vectorization. The hands-on part will illustrate these techniques in the implementation of LU decomposition of small matrices. We will begin demonstrating strip-mining and AVX-512CD in the computation of binning.

Slides:  Colfax_HOW_Series_07.pdf (2 MB) — this file is available only to registered users. Register or Log In.

Session 08
Common Multi-threading Problems

This session talks about common problems in the optimization of multi-threaded applications. We re-visit OpenMP and the binning example from Session 6 to implement multi-threading in that code. The process takes us to the discussion of race conditions, mutexes, efficient parallel reduction with thread-private variables. We also encounter false sharing and demonstrate how it can be eliminated. The second example discussed in this episode represents stencil operations, and the discussion of this example deals with the problem of insufficient parallelism and demonstrates how to move parallelism from vectors to cores using strip-mining and loop collapse.

Slides:  Colfax_HOW_Series_08.pdf (3 MB) — this file is available only to registered users. Register or Log In.

Session 09
Multi-Threading, Memory Aspect

We continue talking about optimization of multi-threading, this time from the memory access point of view. The material includes principles and methods of affinity control and best practices for NUMA architecture, which includes two-way and four-way Xeon processors and Intel Xeon Phi processors in SNC-2/SNC-4 clustering modes. The hands-on part of the episode demonstrates the tuning of matrix multiplication and array copying on a standard processor as well as an Intel Xeon Phi processor and coprocessor.

Slides:  Colfax_HOW_Series_09.pdf (4 MB) — this file is available only to registered users. Register or Log In.

Session 10
Access to Caches and Memory

Memory traffic optimization: how to optimize the utilization of caches, and how to optimally access the main memory. We discuss the requirement of data access locality in space and time and demonstrate techniques for achieving it: unit-stride access, loop fusion, loop tiling and cache-oblivious recursion. We also talk about optimizing memory bandwidth, focusing on the MCDRAM in Intel Xeon Phi processors. The hands-on part demonstrates the application of the discussed methods to the matrix-vector multiplication code.

Slides:  Colfax_HOW_Series_10.pdf (4 MB) — this file is available only to registered users. Register or Log In.

System Requirements (IMPORTANT!)

Get Your System Ready

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To join the webinars:

  • Windows Vista – Windows 10 / Mac OS X 10.6 (Snow Leopard) or later / Google Chrome OS
  • Linux - only with the Google Chrome Browser (Firefox will not work!)
  • Any modern browser for Windows and Mac OS X; Only Google Chrome browser for Linux (Firefox will not work!)
  • 1 Mbps or better Internet connection
  • 2 GB or more RAM
  • Speakers or a headset
  • Recommended: two displays - one for slides, the other for chat and remote access

For remote access:

  • Any recent Linux, Mac OS X, or Windows (additional software required for Windows)
  • 200 Kbps or better Internet connection
  • Allowed outgoing SSH traffic (port 22)

Supplementary Materials

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The course is based on Colfax's book "Parallel Programming and Optimization with Intel Xeon Phi Coprocessors", second edition. All topics discussed in the training are covered in the book. Practical exercises used in the code come with the paper and with the electronic edition. The book is an optional guide for the HOW series training. Members of Colfax Research can get a discount.

Getting Your Questions Answered

At any time, feel free to post your questions at the Colfax Forums. We even have a special forum for HOW series-related discussion.

During the broadcast training sessions, you can ask questions in the chat window shown below. Instructors will respond either immediately, or during a question/answer session.

Chat Logs

  • September 18, 2017 8:20 am - September 29, 2017 9:51 am
  • August 14, 2017 8:10 am - August 24, 2017 12:04 am close

    jinselovejinselove Hi, Jiyuan from Chicago

    atlas7atlas7 Great presentation and demo thank you

    AndreyAndrey Thanks everyone! Session 2 on Tuesday will go into the details of programming Intel Xeon Phi processors and coprocessors.

    jinselovejinselove Hi, I got an email saying that my colfax cluster access is about to expire on August 18, which is a week before the class ends. Can I get any extension?

    sebastiansebastian Thanks Andrey. Interesting lesson. Greetings from Netherlands.

    AndreyAndrey @jinselove I am sorry, it was a mistake in our configuration. Everyone got an extension.

    jinselovejinselove question: how to check how many logical processors I have?

    jinselovejinselove does Xeon E5(Broadwell) have hyper-threading or not?

    jinselovejinselove I ask this because the best computation nodes I have access to at my University is Xeon E5 (we have very limited Xeon phi), so I am wondering what kind of optimization I can still do.

    jinselovejinselove one typical node configuration looks like this: Architecture: x86_64
    CPU op-mode(s): 32-bit, 64-bit
    Byte Order: Little Endian
    CPU(s): 56
    On-line CPU(s) list: 0-27
    Off-line CPU(s) list: 28-55
    Thread(s) per core: 1
    Core(s) per socket: 14
    Socket(s): 2
    NUMA node(s): 2
    Vendor ID: GenuineIntel
    CPU family:

    jinselovejinselove CPU family: 6
    Model: 79
    Model name: Intel(R) Xeon(R) CPU E5-2680 v4 @ 2.40GHz
    Stepping: 1
    CPU MHz: 1200.000
    BogoMIPS: 4806.90
    Virtualization: VT-x
    L1d cache: 32K
    L1i cache: 32K
    L2 cache: 256K
    L3 cache: 35840K
    NUMA node0 CPU(s): 0-13
    NUMA node1 CPU(s):

    sebastiansebastian From my perspective implementing omp is rather simple as compared to vectorizing a loop. For omp one does not need to worry about the length of the loop but just the dependencies inside it. On the other side for vectorizing a loop not only dependencies but also whether i) the data is aligned and ii) the length of the loop has to be considered.

    sebastiansebastian I hope that in the next lessons we can cover the subject i) is data aligned? for example: multidimensional matrices. Fortran and C store matrices differently. what then?. ii) length of loops? multiple of 32? 64? 128?. what to choose?. why?

    sebastiansebastian More on data alignment. What if we have an object?. How can we know whether the data inside the object is aligned?. We could make a proper copy of the data we need, ensure that it is aligned, and then make the loop operate on it instead of in the object elements but then we get a loose in performance normally associated with copying/initialization what is time consuming for large arrays...

    atlas7atlas7 Thanks!

    AndreyAndrey @jinselove E5-2680 v4 does support hyper-threading. However, in your cluster, hyper-threading is disabled in the BIOS ("threads per core:1 "). So you end up with 14*2=28 logical processors, where *2 is for two sockets.

    AndreyAndrey @sebastian We will talk about alignment in Session 7

    atlas7atlas7 I actually watched the session 5 video earlier this week and did some further experiments with various configurations. (e.g. managed to reduce from 16,280 ms serial mode, to 7ms via parallel 256-thread spread over 50 KNL nodes.) Blog article here - enjoy 🙂

AndreyAndrey @atlas7 Could you please re-post the link?

atlas7atlas7 (oops just realised I could not add a link here. let me figure...)

atlas7atlas7 mathalope dot co do

atlas7atlas7 mathalope dot co dot uk

atlas7atlas7 first article at the top

atlas7atlas7 ah thanks! I've also blogged about other sessions / mini experiments too. Within the article I've included a link at the top "Intel Colfax Cluster - Notes - Index Page" where you will be able to see links to other posts. Feel free to validate etc (as I could be wrong in some of the bits and bobs).

sebastiansebastian OK, thanks!

atlas7atlas7 What is the formula that estimates the theoretical peak performance? (For Xeon Phi 2nd Gen aka Knights Landing, according to a deck I've come across is ~3TFLOPS for Double Precision, and ~6TFLOPS for Single Precision). What is the formula that estimates these values?)

atlas7atlas7 My guess is this (not sure if this is correct or not): Peak FLOPS = (Peak Processor Speed) * (Max Number of Threads) * (DP Operations per cycle) = 1.5GHz * 256 Threads * 8 DP Ops per cycle = 3072 GFLOPS

atlas7atlas7 This gives me that ~3 TFLOPS for DP, but I have a feeling this is just a fluke. If there is a a correct formula I would be keen to jot down in my notebook! 🙂

AndreyAndrey For Intel Xeon Phi 7290 (top of the line), use 1.3 GHz (because for AVX workloads, frequency goes down by 200 MHz from the base 1.5 GHz), 72 cores (rather than 256 threads), 8 DP ops per cycle, times 2 instructions per cycle for FMA (due to 2 VPUs per core), times 2 operations per instruction when you are doing FMA (addition and multiplication), for a total of 3000 GFLOP/s.

AndreyAndrey For Xeon Phi 7210 that you have access to use 64 cores and 1.1 GHz for a total of 2250 GFLOP/s

atlas7atlas7 Thanks!

atlas7atlas7 OK I've just documented this GFLOPS estimation formula here: mathalope dot co dot uk /2017/08/21/intel-colfax-cluster-estimate-theoretical-peak-flops-for-intel-xeon-phi-processors/

atlas7atlas7 Question: for Knights Landing Xeon Phi Host processor (e.g. 7210), Should I use the compiler option -xMIC-AVX512 or -xCORE-AVX512? (I'm not sure whether -xMIC-AVX512 only applies to Co-processor).

AndreyAndrey -xMIC-AVX512 is for the bootable version of Intel Xeon Phi processors

AndreyAndrey -xCORE-AVX512 is for Intel Xeon scalable processors (formerly Skylake)

atlas7atlas7 Thanks Andrey! Also, I don't seem to be able to find any documentation on the -DKNLTILE icpc flag (used in the Makefile for lab 4.01). What does it do?

AndreyAndrey This flag defines a preprocessor macro KNLTILE. The macro is used inside the code to define a numerical platform-specific argument (tile size).

AndreyAndrey Look for something like "#ifdef KNLTILE" in the code.

atlas7atlas7 Thanks! Another question (sorry...)... regarding nbody algorithm, at the bottom we have dRate = sqrt( (rate^2)/steps - (rate/steps)^2 ). If we compute this symbolically by hand, dRate should be 0 (since the expression within the sqrt() is 0). Is the goal of this step to compute the numerical error? i.e. the effect of doing a "square then divide" versus "divide then square".

atlas7atlas7 (actually my bad, symbolically it should not be 0. Nevertheless, how does this dRate give us that +/- performance error?)

atlas7atlas7 Ah actually I think I've got it. If nSteps = 10, and skipSteps=3, If I plug into the equation, dRate = sqrt( (7/7)*r^2 - ( 7*r/7)^2 ) = sqrt ( (7/7)*r^2 - (49/49)*r^2 ) = 0. i.e. symbolically dRate should be 0. But when we implement in code, due to multiple uses of "+= and "/=" etc we may get a non 0 result. i.e. the truncation error gets accumulated computationally. So I guess dRate corresponds to the average accumulated "truncation error"?

atlas7atlas7 One more separate note on nbody simulation. In the code we are saying total number of interactions is n*(n-1). But if we look into the MoveParticles function, we actually have performed n*n interactions (including a particle interacting with iteself, remediated with "softening"). Shouldn't the computation of GFLOPS take into account of this? i.e. use n*n instead of n*(n-1), for the computation of "HztoInts" and "HztoGFLOPs"

kbarua1kbarua1 hi, greetings from Calfornia, when we pad for memory access parallelism, arent we worried about the memory space if we have large applications? what is the best way to solve that problem?

AndreyAndrey @kbarua1 Yes, if you pad too much, you risk using too much virtual memory. You should not align every single object, only arrays to which you intend to apply vector instructions.

AndreyAndrey @atlas7 The expression for standard deviation is a standard shortcut used in experimental data analysis. See, for example, http://www.emathzone.com/tutorials/basic-statistics/standard-deviation.html

AndreyAndrey @atlas7 Whether to use n*(n-1) or n*n is a matter of convention, just like the choice of the conversion factor of 20 FLOPs per interaction. For n much greater than 1, the difference between the two expressions is negligible.

atlas7atlas7 @Andrey Super thanks for the clarification! Got it.

  • July 21, 2017 8:00 am - July 25, 2017 9:05 am