Training Calendar

“HOW” Series: Deep Dive

 
June 2017
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    — Upcoming
 

Learn Modern Code

Are you realizing the payoff of parallel processing? Are you aware that without code optimization, computational applications may perform orders of magnitude worse than they are supposed to?

The Web-based HOW Series training provides extensive knowledge needed to extract more of the parallel compute performance potential found in both Intel® Xeon® and Intel® Xeon Phi™ processors and coprocessors.

Practice New Skills

The HOW series is an experiential learning program because comprising instructional and hands-on self-study components:

The instructional part: 10 lecture sessions with 1 hour of theory and 1 hour of practical demonstrations.

In the self-study part: attendees are provided with remote access over SSH to a Linux-based cluster of training server with Intel Xeon Phi processors (KNL) and Intel software development tools.

Receive Certificate

Attendees of these workshops may receive a certificate of completion. The certificate states the Fundamental level of accomplishment in the Parallel Programming Track.

certificate

MC² Series

MC2 Series Banner
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    — Webinar

Regional Trainings

June 2017
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    — New York University

 

Hands-On Developer Training

Intel and Colfax International are offering an updated and expanded hands-on training on code modernization for researchers and engineers in computational disciplines. This training provides the foundation needed to extract more of the parallel compute performance potential found in both Intel® Xeon® and Intel® Xeon Phi™ processors and coprocessors.

Open to Everyone

The course materials and practical exercises are appropriate for developers beginning their journey to parallel programming, with enough detail to also cater to high-performance computing experts.

“HOW” Series: Knights Landing

Knights Landing (KNL) Webinar Banner
This training is available at any time.

 

Optimization for Intel Xeon Phi Processors x200

As the leading provider of code modernization and optimization training, Colfax now offers a hands-on workshop (part of the HOW series) on the best practices for performance optimization for Intel® Xeon Phi processor family x200 (formerly Knights Landing). In this 2-hour webinar we will highlight the new processor features and perform hands-on demonstration of the programming and tuning techniques necessary for achieving the best performance on it.

Another Leap in Parallel Performance

The recently launched Intel Xeon Phi processor family x200 (formerly Knights Landing) boasts 2.5x higher theoretical peak performance and 3.5x higher performance per watt compared to the first generation. With on-board high-bandwidth memory (HBM) and optional integrated high-speed fabric – plus the availability of the bootable (socket) form-factor – these powerful components will transform the fundamental building block of technical computing.

What You Will Learn

The transformation of the scalable manycore coprocessor to a bootable processor is going to be a remarkable development in the parallel computing field and we are offering help to developers worldwide on getting the best out of the new processor. The webinar will help get you up to speed with:

  • Many Integrated Core (MIC) architecture
  • New features in Intel Xeon Phi processor family x200
  • Code porting and modernization strategy

1 Comment on Training Calendar

  1. I’d like to know the schedule of the upcoming regional training courses (Jan/Feb 2017) on parallel compute performance potential found in both Intel® Xeon® and Intel® Xeon Phi™ processors and coprocessors.