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Machine Learning on 2nd Generation Intel® Xeon Phi™ Processors: Image Captioning with NeuralTalk2, Torch

June 20, 2016 // 9 Comments

In this case study, we describe a proof-of-concept implementation of a highly optimized machine learning application for Intel Architecture. Our results demonstrate [...]
Second Edition of “Parallel Programming and Optimization with Intel Xeon Phi Coprocessors”

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Heterogeneous Clustering with Homogeneous Code: Accelerate MPI Applications Without Code Surgery Using Intel Xeon Phi Coprocessors

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Installing Intel MPSS 3.3 in Arch Linux

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Optimization Techniques for the Intel MIC Architecture. Part 1 of 3: Multi-Threading and Parallel Reduction

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Random Articles

Optimization Techniques for the Intel MIC Architecture. Part 3 of 3: False Sharing and Padding

August 8, 2015 // 0 Comments

This is part 3 of a 3-part educational series of publications introducing select topics on optimization of applications for Intel’s multi-core and manycore [...]
Software Developer’s Introduction to the HGST Ultrastar Archive Ha10 SMR Drives

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Delivering a hands-on tutorial at IDF 2015 in San Francisco

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MC² Series: Modern Code Contributed Talks

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Get Ready for Intel’s Knights Landing (KNL) – 3 papers

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