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Articles by Colfax

Get Ready for Intel’s Knights Landing (KNL) – 3 papers

May 11, 2016

2nd generation Intel Xeon Phi processors code-named Knights Landing (KNL) are expected to provide up to 3X higher performance than the 1st generation. With on-board high-bandwidth memory and optional integrated high-speed fabric—plus the availability of socket form-factor — these powerful components will transform the fundamental building block of technical computing. Download three essential publications on new features in Knights Landing Processors: Automatic Vectorization with Intel AVX-512 Instructions in KNL In this document, we focus on the new vector instruction set introduced in Knights Landing processors, Intel® Advanced Vector Extensions 512 (Intel® AVX-512). The discussion includes: Introduction to vector instructions in general, The structure and specifics of AVX-512, and Practical usage tips: checking if a processor has support for various features, compilation process and compiler arguments, pros and cons of explicit and automatic vectorization, using the Intel® C++ Compiler and the GNU Compiler Collection. Download PDF Read Online Clustering Modes in Knights [...]

Slide Deck for Colfax Developer Training on Parallel Programming

February 26, 2016

We are making publicly available the slide deck of the Colfax developer training titled “Parallel Programming and Optimization with Intel Architecture“. This training is an intensive course for developers wishing to leverage the Intel architecture. It is also useful for many-core and multi-core processor programming. The course is based on a book of the same name, which contains targeted exercises (“labs”) for hands-on practicum. In 2014-2015, “Parallel Programming and Optimization…” has visited over 100 locations across the United States: research institutions, government labs, universities, and regional trainings. Over 2000 students attended the course. Many of these events were free to attendees thanks to Intel’s sponsorship. Update: now with new information about the upcoming 2nd generation Intel Xeon Phi processor (Knights Landing, KNL). Slide deck:  Colfax-Developer-Training.pdf (13 MB) (last updated August [...]

Hands-on Developer Training at Rice University

February 17, 2016

We will present our popular Colfax Developer Training on parallel programming and optimization for Intel architecture at Rice University on March 1, 2016. This event is co-hosted by the Ken Kennedy Institute for Information Technology and the Center for Research Computing at Rice University. In this full-day training we will Present our core parallel programming and optimization curriculum Reveal updates for the upcoming 2nd generation Intel Xeon Phi processor architecture codenamed Knights Landing (KNL). Provide remote access to training servers with Intel Xeon Phi coprocessors and an extensive set of original hands-on programming exercises from our book Flyer:  Invite-2016-Xeon-Phi-Training-Series-Rice-University.pdf (624 KB) Slides:  Colfax-Developer-Training.pdf (13 MB) [...]

Meet us at SC15

November 13, 2015

Colfax will be at SC15 in Austin, TX presenting the full spectrum of our products and services, including developer training programs, solutions and components. Sunday (Nov 15) at the Intel HPC Developer Conference: Attend our 3-part hands-on tutorial on the fundamentals of application performance tuning for Intel architecture. The tutorial is at the Omni Austin Hotel Downtown (700 San Jacinto Blvd) in the Congress room. See Intel HPC Developer Conference Web site for agenda and registration. Part 1 at 1:00 – 1:50 pm: multi-threading.  Colfax-SC15-Intel-HPC-Dev-Conf-Hands-on-Lab-Part-1.pdf (2 MB) Part 2 at 2:05 – 2:55 pm: vectorization.  Colfax-SC15-Intel-HPC-Dev-Conf-Hands-on-Lab-Part-2.pdf (2 MB) Part 3 at 3:10 – 4:00 pm: memory tuning.  Colfax-SC15-Intel-HPC-Dev-Conf-Hands-on-Lab-Part-3.pdf (2 MB) We will be providing access to servers with Intel Xeon Phi coprocessors for practical exercises. Code for all exercises: Colfax-Tutorial-SC15-Intel-HPCDevCon.tgz (7 KB) Monday through Thursday (Nov 16-19) on the show floor: Visit us at booth #2023 (right next to [...]

Delivering a hands-on tutorial at IDF 2015 in San Francisco

August 19, 2015

Colfax will be delivering a hands-on lab “Introduction to Programming and Optimization with Intel Xeon and Intel Xeon Phi processors” at IDF. We will run two identical sessions: SFTL003, 9:30 am – 11:30 am, Level 2, Room 2000 SFTL003R, 1:15 am – 3:15 pm, Level 2, Room 2000 The tutorial will feature a presentation (40 minutes) and a practical exercise based on the direct N-body simulation (1 hr 20 [...]

New look, new features of Colfax Research

June 17, 2015

Welcome or welcome back! We have finally completed moving Colfax Research into its new home at The new Web site has the same deep technical content, but now with improved looks. We have also added a membership option. Being a member gives you: Simple and unrestricted access to all papers and downloadable code. No more entering your information multiple times when you want to download multiple files! Brand new forums dedicated to parallel programming and HPC solutions. These forums will be whatever you make them, so feel free to start posting! Newsletter on parallel programming education. If you are already a Newsletter subscriber, go ahead and create a Colfax Research account with the same email address. Your Colfax Research account will be merged with your newsletter subscription. Goodies! (last but not least) For example, right now we are offering a discount of $10 on the purchase of our book to all members. Registration is quick and free. See you [...]

Interview with James Reinders: future of Intel MIC architecture, parallel programming, education

March 5, 2015

A few weeks ago we recorded our conversation with James Reinders, the Director and Chief Evangelist at Intel Corporation. We discussed the future of the parallel programming and Intel MIC architecture products: Intel Xeon Phi coprocessors, Knights Landing (KNL), and future 3rd generation – Knight Hill (KNH). We also talked about how students can learn parallel programming and optimization for high performance applications. Watch the whole interview by clicking the player above, or jump straight to one of the questions in the list below. James Reinders and his role at Intel. – 00:47 Why Parallel Programming and Code Modernization is important? – 01:49 Brief introduction to MIC architecture and Xeon Phi coprocessors. – 04:03 What type of applications benefit from MIC architecture? – 07:16 How to approach porting your code for MIC architecture? – 09:58 What is new in Knights Landing. – 15:24 Details of chip design of Knights Landing. – 19:54 3rd MIC generation – Knights Hill. – 21:16 How to future-proof my code? – 23:15 [...]

Colfax Research papers translated to Japanese

July 14, 2014

With the help of our partners at Intel, some of our articles on Intel Xeon Phi coprocessor programming were translated to the Japanese language. インテル社の協力で、弊社のインテル(R) Xeon Phi(TM) コプロセッサーのプログラミングについての白書の一部が日本語に翻訳されました。 Original: Configuration and Benchmarks of Peer-to-Peer Communication over Gigabit Ethernet and InfiniBand in a Cluster with Intel Xeon Phi Coprocessors Translation:  JP-Colfax_InfiniBand_for_MIC.pdf (2 MB) Original: Heterogeneous Clustering with Homogeneous Code: Accelerate MPI Applications Without Code Surgery Using Intel Xeon Phi Coprocessors Translation:  JP-Colfax_Heterogeneous_Clustering_Xeon_Phi.pdf (657 KB) Original: Multithreaded Transposition of Square Matrices with Common Code for Intel Xeon Processors and Intel Xeon Phi Coprocessors Translation:  JP-Colfax_Transposition-7110P.pdf (987 KB) Original: Test-driving Intel Xeon Phi coprocessors with a basic N-body simulation Translation:  JP-Colfax_Nbody_Xeon_Phi-with-addendum.pdf (2 [...]
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