Regional Trainings Begin for 2017

February 8, 2017

We are resuming our regional hands-on training on parallel programming and optimization at major universities across the United States. This year, in addition to teaching performance tuning on Intel Architecture, our program will include Hands-on exercises on our new Colfax Cluster with Intel Xeon Phi processors x200 and Information about machine learning on Intel Architecture Our first stop is Yale University on February 22-23. For future events, watch our Regional Training [...]

Meet us at SC16

November 8, 2016

If you are going to the SC16 conference, visit Colfax: At the Intel HPC Developer Conference (free pre-SC16 event) When: on Sunday, November 13, 2016, at 9:45 am – 10:35 am Where: Sheraton Salt Lake City Hotel Event: Technical session “Optimizing Machine Learning Workloads on Intel Platforms” On the SC’16 exhibition floor When: Monday, November 14 through Thursday, November 16 Where: Colfax’s booth #2407 Event: See the Ninja Developer Platform based on Intel Xeon Phi processors and all other components of Intel Scalable System Framework. Stop by for a live demo of code modernization and play with a machine learning application that describes you and the scene around you with words. At the Intel Community Hub When: Wednesday, November 16, at 10:15 am Where: Intel’s booth #1819 Event: Code Modernization Sharing by the Ecosystem Community [...]

Hands-on Developer Training at Rice University

February 17, 2016

We will present our popular Colfax Developer Training on parallel programming and optimization for Intel architecture at Rice University on March 1, 2016. This event is co-hosted by the Ken Kennedy Institute for Information Technology and the Center for Research Computing at Rice University. In this full-day training we will Present our core parallel programming and optimization curriculum Reveal updates for the upcoming 2nd generation Intel Xeon Phi processor architecture codenamed Knights Landing (KNL). Provide remote access to training servers with Intel Xeon Phi coprocessors and an extensive set of original hands-on programming exercises from our book Flyer: Invite-2016-Xeon-Phi-Training-Series-Rice-University.pdf (624 KB) Slides:  Colfax-Developer-Training.pdf (12 MB) — this file is available only to registered users. Register or Log In. [...]

Meet us at SC15

November 13, 2015

Colfax will be at SC15 in Austin, TX presenting the full spectrum of our products and services, including developer training programs, solutions and components. Sunday (Nov 15) at the Intel HPC Developer Conference: Attend our 3-part hands-on tutorial on the fundamentals of application performance tuning for Intel architecture. The tutorial is at the Omni Austin Hotel Downtown (700 San Jacinto Blvd) in the Congress room. See Intel HPC Developer Conference Web site for agenda and registration. Part 1 at 1:00 – 1:50 pm: multi-threading.  Colfax-SC15-Intel-HPC-Dev-Conf-Hands-on-Lab-Part-1.pdf (2 MB) — this file is available only to registered users. Register or Log In. Part 2 at 2:05 – 2:55 pm: vectorization.  Colfax-SC15-Intel-HPC-Dev-Conf-Hands-on-Lab-Part-2.pdf (2 MB) — this file is available only to registered users. Register or Log In. Part 3 at 3:10 – 4:00 pm: memory tuning.  Colfax-SC15-Intel-HPC-Dev-Conf-Hands-on-Lab-Part-3.pdf (2 MB) — this file is available only to registered users. Register or Log In. We will be providing access to [...]

Delivering a hands-on tutorial at IDF 2015 in San Francisco

August 19, 2015

Colfax will be delivering a hands-on lab “Introduction to Programming and Optimization with Intel Xeon and Intel Xeon Phi processors” at IDF. We will run two identical sessions: SFTL003, 9:30 am – 11:30 am, Level 2, Room 2000 SFTL003R, 1:15 am – 3:15 pm, Level 2, Room 2000 The tutorial will feature a presentation (40 minutes) and a practical exercise based on the direct N-body simulation (1 hr 20 [...]

Are You Realizing the Payoff of Parallel Processing?

July 10, 2015

My contributed article has just been published at Intel Communities. …as Intel processor architectures evolve, you get performance boosts in some areas without doing anything with your code. For instance, such architectural improvements as bigger caches, instruction pipelining, smarter branch prediction, and prefetching improve performance of some applications without any changes in the code. However, parallelism is different. To realize the full potential of the capabilities of multiple cores and vectors, you have to make your application aware of parallelism. That is what code modernization is about: it is the process of adapting applications to new hardware capabilities, especially parallelism on multiple levels. … Once you have a robust version of code, you are basically future-ready. You shouldn’t have to make major modifications to take advantage of new generations of the Intel architecture. Just like in the past, when computing applications could “ride the wave” of increasing clock frequencies, your modernized code will be able to automatically take [...]

Colfax visits IPCC at Hartree Centre

June 25, 2015

In the second week of our visit to Intel Performance Computing Centres (IPCC) in the U.K., we visited the IPCC at Hartree Centre. Our work involved conducting our 1-Day CDT on Monday, and then investigating scientific applications for optimization opportunities for the remaining 4 days. We investigated two applications; a molecular dynamics simulation called DL_MESO and weather simulation called Harmonie. With the help of Intel tools such as Intel VTune Amplifier, we profiled and analysed these applications for possible optimizations. For the DL_MESO application, we had the fortune of working with Michael Seaton, the primary author of DL_MESO, and together we took the Lattice-Boltzmann part of the DL_MESO application and sped it up by 45.5% on a server node based on an Intel Xeon CPU. We plan to continue collaborating with Hartree team on DL_MESO and further optimize [...]

New look, new features of Colfax Research

June 17, 2015

Welcome or welcome back! We have finally completed moving Colfax Research into its new home at The new Web site has the same deep technical content, but now with improved looks. We have also added a membership option. Being a member gives you: Simple and unrestricted access to all papers and downloadable code. No more entering your information multiple times when you want to download multiple files! Brand new forums dedicated to parallel programming and HPC solutions. These forums will be whatever you make them, so feel free to start posting! Newsletter on parallel programming education. If you are already a Newsletter subscriber, go ahead and create a Colfax Research account with the same email address. Your Colfax Research account will be merged with your newsletter subscription. Goodies! (last but not least) For example, right now we are offering a discount of $10 on the purchase of our book to all members. Registration is quick and free. See you [...]

Working with the Edinburgh Parallel Computing Center

June 17, 2015

We spent 5 days visiting the Edinburgh Parallel Computing Center the week of June 8, 2015. Our job was to assist this organization, selected as an IPCC in 2014, with the optimization of a molecular dynamics code CP2K. Our host, Adrian Jackson, was so kind as to report on our collaboration in his blog: day 1, day 2, day 3, day 4 and day 5. This week we are continuing our trip in the UK collaborating with another IPCC at the Hartree [...]