Performance

“HOW Series”: Webinars on Performance Optimization, June 2017

April 28, 2017

  In a Nutshell HOW Series “Deep Dive” is a free 20-hour hands-on in-depth training on parallel programming and performance optimization in computational applications on Intel architecture. The 6th run in 2017 begins June 19, 2017. Broadcasts start at 16:00 GMT (9:00 am in San Francisco, 12:00 noon in New York, 5:00 pm in London, 7:00 pm in Moscow, 9:30 pm in New Delhi, 1:00 am in Tokyo). June 2017 S M T W H F S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30                   — Webinar+remote access c GMT 16:00 San Francisco 9:00 am New York 12:00 noon London 5:00 pm Moscow 7:00 pm New Delhi 9:30 pm Tokyo 1:00 am Live status as of 17 minutes ago: 94 registrants. Register Cannot attend? Register anyway for cluster access, progress updates and recorded video.   Learn More Why Attend the HOW Series Course Roadmap Instructor Bio Prerequisites Remote Access for Hands-On Exercises Slides, Code and Video System Requirements (IMPORTANT!) Supplementary Materials Chat Why Attend the [...]

HOW Series “Deep Dive”: Webinars on Performance Optimization, May 2017

April 13, 2017

  In a Nutshell HOW Series “Deep Dive” is a free 20-hour hands-on in-depth training on parallel programming and performance optimization in computational applications on Intel architecture. The 5th run in 2017 begins May 15, 2017. Broadcasts start at 16:00 GMT (9:00 am in San Francisco, 12:00 noon in New York, 5:00 pm in London, 7:00 pm in Moscow, 9:30 pm in New Delhi, 1:00 am in Tokyo). May 2017 S M T W H F S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31                   — Webinar+remote access GMT 16:00 San Francisco 9:00 am New York 12:00 noon London 5:00 pm Moscow 7:00 pm New Delhi 10:30 pm Tokyo 1:00 am Live status as of 32 days ago: 100 registrants. Register Registration for this training in June 2017 is also open. Cannot attend? Register anyway for cluster access, progress updates and recorded video.   Learn More Why Attend the HOW Series Course Roadmap Instructor Bio Prerequisites Remote Access for Hands-On Exercises Slides, Code and Video System Requirements [...]

HOW Series “Deep Dive”: Webinars on Performance Optimization, March 2017

February 15, 2017

  In a Nutshell HOW Series “Deep Dive” is a free 20-hour hands-on in-depth training on parallel programming and performance optimization in computational applications on Intel architecture. The 3rd run in 2017 begins March 13, 2017. Broadcasts start at 16:00 UTC (9:00 am in San Francisco, 12:00 noon in New York, 4:00 pm in London, 7:00re pm in Moscow, 9:30 pm in New Delhi, 1:00 am in Tokyo). March 2017 S M T W H F S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31                   — Webinar+remote access UTC 16:00 San Francisco 9:00 am New York 12:00 noon London 4:00 pm Moscow 7:00 pm New Delhi 9:30 pm Tokyo 1:00 am Live status as of 95 days ago: 138 registrants. Registration for this workshop is closed, but you can register for the April HOW Series.   Learn More Why Attend the HOW Series Course Roadmap Instructor Bio Prerequisites Remote Access for Hands-On Exercises Slides, Code and Video System Requirements (IMPORTANT!) Supplementary Materials Chat Why Attend the HOW [...]

MC² Series: Modern Code Contributed Talks

February 10, 2017

In Modern Code Contributed Talks, or MC² Series, experts in computational disciplines share their experience. Register for these ongoing webinars to learn the performance optimization methods used in real-life applications. Would you like to contribute a talk? Contact us. Scholarship is available in the form of access to a diverse collection of powerful computing platforms. More Information MC² 005: Computational Biology Speaker: Pablo González de Aledo Marugán, Imperial College of London Title: An optimization approach for the computational modeling of biological development Date: July 13, 2017 at 16:00-17:00 GMT [...]

Machine Learning on 2nd Generation Intel® Xeon Phi™ Processors: Image Captioning with NeuralTalk2, Torch

June 20, 2016

  In this case study, we describe a proof-of-concept implementation of a highly optimized machine learning application for Intel Architecture. Our results demonstrate the capabilities of Intel Architecture, particularly the 2nd generation Intel Xeon Phi processors (formerly codenamed Knights Landing), in the machine learning domain. Download as PDF:  Colfax-NeuralTalk2-Summary.pdf (814 KB) — this file is available only to registered users. Register or Log In. or read online below. Code: see our branch of NeuralTalk2 for instructions on reproducing our results (in Readme.md). It uses our optimized branch of Torch to run efficiently on Intel architecture. See also: colfaxresearch.com/get-ready-for-intel-knights-landing-3-papers/ 1. Case Study It is common in the machine learning (ML) domain to see applications implemented with the use of frameworks and libraries such as Torch, Caffe, TensorFlow, and similar. This approach allows the computer scientist to focus on the learning algorithm, leaving the details of performance optimization to the framework. Similarly, the ML [...]