Crash Course on Programming and Optimization with Intel Xeon Phi Coprocessors at SC14

Programming and optimization of applications for Intel Xeon Phi processors is going to be discussed in more than ten presentations in four concurrent track sessions at the Intel HPC Developer Conference at SC14 in New Orleans, LA on November 16, 2014.

Colfax has contributed two of these presentations: one a crash course on the applicability domain and programming models for Intel Xeon Phi coprocessors, and another a demonstration of optimization of an N-body simulation for coprocessors on the node level and cluster level. Slides of our presentations can be downloaded from this page. Stay tuned for an upcoming Colfax Research paper with downloadable code for the example demonstrated in our slides.

If you are attending SC14 in New Orleans, visit us at Colfax’s booth 1047 and also at the Intel Channel Pavilion.

Part 1. Introduction, Programming Models:  Colfax-Intro.pdf (10 MB) — this file is available only to registered users. Register or Log In.

Part 2. Optimization Techniques:  Colfax-Optimization.pdf (9 MB) — this file is available only to registered users. Register or Log In.