Optimization for Intel Architecture and Machine Learning

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Date
Wednesday, February 22, 2017 - Thursday, February 23, 2017
9:00 am - 4:00 pm (day 2 ends at 12:30 pm)

Location
Yale Center for Research Computing
160 St Ronan Street, New Haven, CT, 06511, YCRC Auditorium

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Parallel Programming and Optimization for Intel® Architecture

Intel Architecture Lineup

Intel and Colfax International are offering an updated and expanded hands-on training on code modernization for researchers and engineers in computational disciplines. This training provides the foundation needed to extract more of the parallel compute performance potential found in both Intel® Xeon® and Intel® Xeon Phi™ processors and coprocessors. The course materials and practical exercises are appropriate for developers beginning their journey to parallel programming, with enough detail to also cater to high-performance computing experts.


Attendance

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The training is conducted by Colfax International.
Registration is open to everyone free of charge thanks to Intel’s sponsorship.


Hands-On Component

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Colfax Developer Training is far more than a lecture – it is an experiential learning program. That is because the training contains hands-on component in two forms:

  1. The instructor will demonstrate the methods taught in the course live, on servers with the latest Intel Xeon and Intel Xeon Phi processors.
  2. Attendees will receive remote access to training servers with Intel Xeon E5 series processors, Intel Xeon Phi processors (KNL) and coprocessors (KNC) for 2 days and a set of programming and optimization exercises.

Bring your own laptop to take advantage of this opportunity.


Agenda

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Day 1 – Optimization

  • Check-in (9:00 – 9:30 am)
    + cluster access setup, light breakfast
  • Morning session (9:30 am – 12:00 noon)
    • Sneak Peak: What is covered today (30 min)
    • Optimization Example (2 hours)
      • Demonstration: direct N-body
      • Intel processor architectures
      • Task and data parallelism
      • Memory organization
      • Programming coprocessors, clusters
  • Lunch (12:00 noon – 12:30 pm)
  • Afternoon session (12:30 pm – 4:00 pm)
    • Optimization Pointers (1.5 hours)
      • Scalar tuning with Intel compilers
      • Automatic vectorization
      • Multi-threading with OpenMP
      • Cache usage and memory access
      • Communication control
    • Intel Xeon Phi processors (1 hour)
      • Compiling with AVX-512
      • Using high-bandwidth memory
      • Leveraging clustering modes
      • Coprocessor form-factor and KNL-F
    • Cluster computing (1 hour)
      • Requesting resources
      • Using Intel Omni-Path Architecture
      • MPI Performance Snapshot
      • Practical example

Day 2 – Machine Learning

  • Check-in (9:00 – 9:30 am)
    + cluster access setup, light breakfast
  • Morning session (9:30 am – 12:30 pm)
    • Machine learning and DNNs
    • Future of AI on IA
    • Intel Python and DNNs
    • Intel-optimized frameworks
  • Event ends at 12:30 pm

Day 1 Slides:  Colfax_Developer_Training_Slides_Yale_Feb_17 (12 MB) — this file is available only to registered users. Register or Log In.
Day 2 Slides:  Colfax_Machine_Learning_Presentation (5 MB) — this file is available only to registered users. Register or Log In.


Registration

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